<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
  <head>
    <title>ERRDEVID</title>
    <link href="insn.css" rel="stylesheet" type="text/css"/>
  </head>
  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ERRDEVID, Device Configuration Register</h1><p>The ERRDEVID characteristics are:</p><h2>Purpose</h2>
        <p>Provides discovery information for the component.</p>
      <h2>Configuration</h2>
        <p>ERRDEVID is implemented only as part of a memory-mapped group of error records.</p>
      <h2>Attributes</h2>
        <p>ERRDEVID is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="10"><a href="#fieldset_0-31_22">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-21_21-1">PFG</a></td><td class="lr" colspan="1"><a href="#fieldset_0-20_20">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">IRQCR</a></td><td class="lr" colspan="16"><a href="#fieldset_0-15_0">NUM</a></td></tr></tbody></table><h4 id="fieldset_0-31_22">Bits [31:22]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-21_21-1">PFG, bit [21]<span class="condition"><br/>When RAS System Architecture v2 is implemented:
                        </span></h4><div class="field">
      <p>Common Fault Injection Mechanism. Describes whether any Common Fault Injection Mechanism registers are implemented in the same page as this register. Defined values are:</p>
    <table class="valuetable"><tr><th>PFG</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Any Common Fault Injection Mechanism registers are implemented in the same page as this register.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Any Common Fault Injection Mechanism registers are implemented in a separate fault injection group page.</p>
        </td></tr></table><p>Accessing this field has the following behavior:</p><ul><li>When ERRDEVID is part of a fault injection group, access to this field
                            is <span class="access_level">RAZ/WI</span>.</li><li>
                Otherwise,
                
            access to this field
            is <span class="access_level">RO</span>.</li></ul></div><h4 id="fieldset_0-21_21-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, RAZ.</p>
    </div><h4 id="fieldset_0-20_20">Bit [20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_16">IRQCR, bits [19:16]</h4><div class="field">
      <p>Interrupt Control registers. Describes whether the interrupt control registers are implemented. Defined values are:</p>
    <table class="valuetable"><tr><th>IRQCR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether any interrupt control registers are implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>An <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> form of interrupt control registers are implemented.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>The recommended layout form of interrupt control registers are implemented, for simple interrupts.</p>
        </td></tr><tr><td class="bitfield">0b0011</td><td>
          <p>The recommended layout form of interrupt control registers are implemented, for message-signaled interrupts.</p>
        </td></tr><tr><td class="bitfield">0b1111</td><td>
          <p>Interrupt control registers are not implemented.</p>
        </td></tr></table>
      <p>All other values are reserved.</p>
    <p>Accessing this field has the following behavior:</p><ul><li>When ERRDEVID is part of a RAS agent that is not a System RAS agent, access to this field
                            is <span class="access_level">RAO/WI</span>.</li><li>When ERRDEVID is part of a fault injection group, access to this field
                            is <span class="access_level">RAZ/WI</span>.</li><li>
                Otherwise,
                
            access to this field
            is <span class="access_level">RO</span>.</li></ul></div><h4 id="fieldset_0-15_0">NUM, bits [15:0]</h4><div class="field">
      <p>Highest numbered index of the error records in this group, plus one. Each implemented record is owned by a node. A node might own multiple records.</p>
    <p>This manual describes a group of error records accessed via a standard 4KB memory-mapped peripheral. For a 4KB peripheral, up to 24 error records can be accessed if the Common Fault Injection Model is implemented, and up to 56 otherwise.</p>
<p>This field has an <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> value.</p><p>Access to this field is <span class="access_level">RO</span>.</p></div><h2>Accessing ERRDEVID</h2><h4>ERRDEVID can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>RAS</td><td><span class="hexnumber">0xFC8</span></td><td>ERRDEVID</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
</html>
